Low power and reduced area Carry Select Adder

Power dissipation is one of the most important design objectives in integrated circuits, after speed. As adders are the most widely used components in such circuits, design of efficient adder is of much concern for researchers.From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a fewer transistors to significantly reduce the area and power of the CSLA. Based on this modification 16-bit, square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18-um Tanner Tool vs13.0 CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.